Offline pin planning for hardware bring-up

Logichart

Plan microcontroller, FPGA, and connector pinouts offline, assign logical signals to real physical pins, and catch bank, capability, and differential-pair conflicts before you wire anything.

iPhone + iPadOffline workspaceDeterministic checksNo account, no tracking

From part to pin map

Assign every signal, check every pin

A project targets one device with a full set of pins. Capture which logical signal lands on which physical pin, then run a deterministic design-rule engine over the plan. The illustrations below show the concept model; the app renders your own devices and results.

BOARD 48-PIN MCU · BANK1 3.3V · BANK2 1.8V A1PWR A2GND A3UART_TX A4UART_RX A5GPIO A6ADC0 B1SPI_SCK B2SPI_MOSI B3SPI_MISO B4I2C B5CLK B6GPIO C1LVDS0_P C2LVDS0_N C3SWDIO C4SWCLK C5NC C6GPIO accent = assigned signal · amber = power · blue = reserved debug · outline = free
Illustration: the pin-map grid links each physical pin to its bank, voltage domain, and capabilities, and shows the logical signal assigned to it.
DESIGN-RULE REPORT 2 blocking · 1 warning · deterministic Double-assigned pin — A3UART_TX and a second net both target A3 Bank voltage conflict — BANK13.3 V and 1.8 V signals required in one bank Reserved pin overwritten — C3SWDIO reassigned to a GPIO net Differential pair valid — LVDS0C1/C2 are an adjacent P/N pair in BANK2
Illustration: the checker flags double-assignment, capability mismatch, bank voltage conflicts, reserved-pin protection, differential-pair validity, capacity, and completeness.

What Logichart does

A focused pin-planning workspace

Every value comes from the plan you enter. Logichart records assignments and checks them against the part's rules; it does not sign off a design, replace a datasheet, or connect to a vendor tool.

Model a real device

One project targets one device. Each pin carries a physical designator, an IO bank and voltage domain, and its capabilities: power, ground, GPIO, ADC, DAC, PWM, UART, SPI, I2C, CAN, USB, clock, reset, JTAG/SWD, differential, no-connect.

Assign signals to pins

Define the logical signals you need to route, each with a required capability and an optional differential flag, then assign them across the live pin-map grid.

Deterministic checks

A design-rule engine flags double-assigned pins, capability mismatches, power and no-connect misuse, incompatible bank voltages, invalid differential pairs, bank IO overflows, overwritten reserved debug pins, and incomplete nets.

Reproducible auto-assign

A first-fit auto-assigner places remaining signals on compatible free pins while honoring bank and voltage rules. No randomness and no network, so the same plan always produces the same result.

Bundled device library

Authored example devices — a 48-pin MCU, a small two-bank FPGA, a 40-pin GPIO header, and a board connector — make the app usable the moment it launches. No downloads, no account.

Local ledger and export

Review plan history and check results, and export a text pin map and net list through the system share sheet. Everything stays in the app's local container.

The eight checks

What the design-rule engine verifies

Each plan is evaluated the same way every time. Severities separate blocking conflicts from advisory notes and completeness.

Double-assignmentTwo signals cannot share one physical pin.
Capability mismatchA pin must be able to provide the signal's required function.
Power / ground / no-connect misuseReserved-function pins are not used as ordinary IO.
Bank voltage conflictOne IO bank cannot carry incompatible voltage domains.
Differential-pair validityP and N sit on a real adjacent pair within one bank.
Bank IO capacityAssigned IO stays within the bank's available IO pins.
Reserved-pin protectionJTAG/SWD and reset pins are not silently overwritten.
CompletenessAll signals are placed and all required nets are present.

Read this first

A planning aid, not an electrical sign-off tool

Logichart is a planning and documentation aid. It does not replace the manufacturer datasheet, a vendor pin-mux tool such as STM32CubeMX, Vivado, or Quartus, timing or signal-integrity analysis, or a board-level ERC/DRC.

Bundled device templates are illustrative, not authoritative part models. You are responsible for verifying every assignment against the official datasheet before committing a design.